Palavras Chaves: cálculo de perdas, Conversores CC-CC, Eletrônica de Potência
Resumo
O aumento da frequência de comutação
vem sendo utilizada para aumentar a densidade
volumétrica de potência em conversores estáticos. Assim,
diversos trabalhos científicos tem apresentado estudos
relacionados aos impactos dos elementos parasitas no
layout de placa de circuito impresso (PCB) de conversores
estáticos CC/CC, comparações entre as tecnologias de
semicondutores, desenvolvimento de equações analíticas
para a determinação das perdas nos elementos e a
utilização de softwares de simulações na determinação de
elementos parasitas de conversores estáticos comutados
em altas frequências. Desta forma, o presente trabalho
apresenta uma metodologia de quantificação de perdas
elétricas em chaves semicondutoras de conversores
estáticos devido aos elementos parasitas presentes na PCB.
Através da utilização de técnicas de engenharia assistida
por computador e simulações SPICE, a metodologia
proposta tem como objetivos apresentar uma estimativa
de perdas devido às ressonâncias causadas pelos elementos
parasitas e auxiliar no processo da prototipação, voltada
para a redução de perdas dos dispositivos semicondutores
presentes na PCB de um conversor estático. Para a
validação da metodologia implementou-se um conversor
boost síncrono comutado em 350kHz e com potência
nominal de 100W. Resultados teóricos, de simulações e
experimentais são apresentados.
Title: METHOD FOR QUANTIFICATION OF SEMICONDUCTOR POWER LOSSES IN POWER CONVERTERS DUE TO PRINTED CIRCUIT BOARD PARASITE ELEMENTS
Keywords: DC-DC Converters, losses calculation, Power Electronics
Abstract
The switching frequency rising has been
applied in order to maximize volumetric power density in
power converters. Many scientific papers discuss about
the parasite elements impact in DC/DC high frequency
power converters, comparison between semiconductors
technologies, the importance of instrumentation in
high frequencies, development of analytic equations to
modelling the power losses in the elements and the use
of softwares in order to identify and quantify parasite
elements in power converters. Thus, this work presents a
semiconductors power losses quantification methodology
in power converters due to the printed circuit boards
parasite (PCB) elements. Through the utilization of
computer aided design techniques and SPICE simulation,
the proposed methodology aims to present a power losses
estimation due to parasite elements ressonance, focused to
reduce semiconductor losses in the power converter PCB.
In order to validate the proposed methodology a prototype
of the synchronous boost converter switched in 350kHz and
100W of nominal power was implemented. Theoretical,
simulation and practical results are presented, validating
the proosed methodology.
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