Revista Eletrônica de Potência (Brazilian Journal of Power Electronics)

Palavras Chaves: Algoritmo de Equalização, Algoritmo de Ordenação, Conversor Multinível Modular, Simulação em tempo real

Resumo

Este artigo apresenta um estudo comparativo de estratégias usadas para ordenar e selecionar os submódulos de um conversor multinível modular em função das tensões CC dos seus capacitores. Estes conversores foram propostos para aplicações em alta tensão devido a possibilidade da expansão do número de módulos permitindo obter tensões elevadas em seus terminais de saída. Além da modularidade, a síntese de tensões com múltiplos níveis permite que eles sejam conectados a rede sem estruturas magnéticas complexas ou filtros harmônicos de ordem elevada. Resultados de simulação em tempo real são apresentados para validar as estratégias de equalização investigadas e demonstrar o desempenho dos algoritmos implementados no processador digital de sinais. Finalmente, resultados experimentais obtidos com um protótipo em pequena escala, com três submódulos por polo, são apresentados para validar os resultados da simulação em tempo real.

Title: Real Time Simulation Of Dc Voltage Equalization Algorithms Of A Multilevel Modular Converter

Keywords: Equalization Algorithm, Modular Multilevel Converter, Real Time Simulation, Sort Algorithm

Abstract

This paper presents a comparative study of different strategies used to sort and select the submodules of a modular multilevel converters according to their capacitor DC voltages. These converters have been initially proposed for high voltage applications due to the possibility to expand the number of modules allowing high-voltage levels at the converter output terminals. Besides the modularity, the synthesis of multilevel voltages allow them to be connected to the mains without complex magnetic structures or high-order harmonic filters. Real time simulation results are used to validated the control strategies investigated and to demonstrate the performance of the algorithms implemented on a digital signal processor. Finally, experimental results obtained with a small-scale prototype with 6 submodules per branch are presented to validate the real time simulation results.

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